3-d sram array to improve stability and performance

Abstract

A design structure for a three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier on an additional chips or chips overlying the memory array. Freedom of placement of such peripheral circuits is provided with minimal increase in connection length since word line decoders may be placed is general registration with any location along the word lines while local evaluation circuits and/or sense amplifiers can be placed at any location generally in registration with the bit line(s) to which they correspond.