The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2010

Filed:

Apr. 21, 2008
Applicants:

Nobukatsu Saito, Kawasaki, JP;

Masaharu Minamizawa, Kawasaki, JP;

Yoshiyuki Yoneda, Kawasaki, JP;

Nobutaka Shimizu, Kawasaki, JP;

Kazuyuki Imamura, Kawasaki, JP;

Atsushi Kikuchi, Kawasaki, JP;

Tadahiro Okamoto, Kawasaki, JP;

Eiji Watanabe, Kawasaki, JP;

Inventors:

Nobukatsu Saito, Kawasaki, JP;

Masaharu Minamizawa, Kawasaki, JP;

Yoshiyuki Yoneda, Kawasaki, JP;

Nobutaka Shimizu, Kawasaki, JP;

Kazuyuki Imamura, Kawasaki, JP;

Atsushi Kikuchi, Kawasaki, JP;

Tadahiro Okamoto, Kawasaki, JP;

Eiji Watanabe, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.


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