The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Apr. 24, 2006
Applicants:

Masahiro Takeda, Hamamatsu, JP;

Kazuhiro Hotta, Hamamatsu, JP;

Inventors:

Masahiro Takeda, Hamamatsu, JP;

Kazuhiro Hotta, Hamamatsu, JP;

Assignee:

Hamamatsu Photonics K.K., Hamamatsu-shi, Shizuoka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A failure analysis apparatusis composed of an inspection information acquirerfor acquiring at least a pattern image Pof a semiconductor device, a layout information acquirerfor acquiring a layout image P, a failure analyzerfor analyzing a failure of the semiconductor device, and an analysis screen display controllerfor letting a display devicedisplay information about the failure analysis. The analysis screen display controllergenerates a superimposed image in which the pattern image Pand the layout image Pare superimposed, as an image of the semiconductor device to be displayed by the display device, and sets a transmittance of the layout image Prelative to the pattern image Pin the superimposed image. This substantializes a semiconductor failure analysis apparatus, analysis method, analysis program, and analysis system capable of securely and efficiently carrying out the analysis of the failure of the semiconductor device.


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