The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Jun. 06, 2006
Applicants:

Rakesh Dodeja, Portland, OR (US);

Neelam Chandwani, Portland, OR (US);

Chetan Hiremath, Portland, OR (US);

Udayan Mukherjee, Portland, OR (US);

Anthony Ambrose, Portland, OR (US);

Inventors:

Rakesh Dodeja, Portland, OR (US);

Neelam Chandwani, Portland, OR (US);

Chetan Hiremath, Portland, OR (US);

Udayan Mukherjee, Portland, OR (US);

Anthony Ambrose, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.


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