The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2010
Filed:
Dec. 05, 2008
Akira Ide, Tokyo, JP;
Yasuhiro Takai, Tokyo, JP;
Akira Kotabe, Hino, JP;
Tomonori Sekiguchi, Tama, JP;
Riichiro Takemura, Los Angels, CA (US);
Satoru Akiyama, Kokubunji, JP;
Akira Ide, Tokyo, JP;
Yasuhiro Takai, Tokyo, JP;
Akira Kotabe, Hino, JP;
Tomonori Sekiguchi, Tama, JP;
Riichiro Takemura, Los Angels, CA (US);
Satoru Akiyama, Kokubunji, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A timing control circuit DLYreceives clock signal CKa with period Tand activation signal ACT and outputs fine timing signal FT with delay of m*T+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLYcomprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*Tmeasured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.