The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2010
Filed:
May. 01, 2007
Gauri V. Karve, Austin, TX (US);
Debby Eades, Manor, TX (US);
Gregory S. Spencer, Pflugerville, TX (US);
Ted R. White, Austin, TX (US);
Gauri V. Karve, Austin, TX (US);
Debby Eades, Manor, TX (US);
Gregory S. Spencer, Pflugerville, TX (US);
Ted R. White, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor process and apparatus provides a planarized hybrid substrate () by removing a nitride mask layer () and using an oxide polish stop layer () when an epitaxial semiconductor layer () is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack () is formed which includes one or more oxide polish stop layers () formed between the SOI semiconductor layer () and a nitride mask layer (). The oxide polish stop layer () may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.