The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2010

Filed:

Apr. 10, 2009
Applicants:

Fayez E. Abboud, Pleasanton, CA (US);

Sriram Krishnaswami, Saratoga, CA (US);

Benjamin M. Johnston, Los Gatos, CA (US);

Hung T. Nguyen, Fremont, CA (US);

Matthias Brunner, Kirchheim, DE;

Ralf Schmid, Poing, DE;

John M. White, Hayward, CA (US);

Shinichi Kurita, San Jose, CA (US);

James C. Hunter, Los Gatos, CA (US);

Inventors:

Fayez E. Abboud, Pleasanton, CA (US);

Sriram Krishnaswami, Saratoga, CA (US);

Benjamin M. Johnston, Los Gatos, CA (US);

Hung T. Nguyen, Fremont, CA (US);

Matthias Brunner, Kirchheim, DE;

Ralf Schmid, Poing, DE;

John M. White, Hayward, CA (US);

Shinichi Kurita, San Jose, CA (US);

James C. Hunter, Los Gatos, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for testing a plurality of electronic devices formed on a large area substrate is described. In one embodiment, the apparatus performs a test on the substrate in one linear axis in at least one chamber that is slightly wider than a dimension of the substrate to be tested. Clean room space and process time is minimized due to the smaller dimensions and volume of the system.


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