The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
Apr. 28, 2009
Wen-hsun Lo, Hsinchu County, TW;
Hsing-chao Liu, Hsinchu County, TW;
Jin-dong Chern, Taoyuan County, TW;
Kwang-ming Lin, Hsinchu, TW;
Wen-Hsun Lo, Hsinchu County, TW;
Hsing-Chao Liu, Hsinchu County, TW;
Jin-Dong Chern, Taoyuan County, TW;
Kwang-Ming Lin, Hsinchu, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer are sequentially formed. A bond pad is formed over the second interlayer dielectric layer in a second device region of the semiconductor structure. A passivation layer is formed over the bond pad and the second interlayer dielectric layer. A first etching process is performed to form a first opening in the first device region and a second opening in the second device region, wherein the first opening exposes a portion of the second interlayer dielectric layer over the fuse element and, and the second opening partially exposes a portion of the bond pad. A second etching process and a third etching process are performed to leave another passivation layer conformably covering the fuse element and the semiconductor structure adjacent thereto.