The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2010

Filed:

Dec. 14, 2005
Applicants:

Ruiqi Tian, Austin, TX (US);

Willard E. Conley, Austin, TX (US);

Mehul D. Shroff, Austin, TX (US);

Inventors:

Ruiqi Tian, Austin, TX (US);

Willard E. Conley, Austin, TX (US);

Mehul D. Shroff, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.


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