The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2010
Filed:
Nov. 22, 2006
Mitchell G. Poplack, San Jose, CA (US);
Steven Comfort, Poughkeepsie, NY (US);
Mitchell G. Poplack, San Jose, CA (US);
Steven Comfort, Poughkeepsie, NY (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method and apparatus for designing a processor-based emulation integrated circuit (chip) having a selectable fastpath topology. Included are initially designing an N-level fastpath topology comprising a plurality of processors, then reducing the N-level fastpath topology to an M-level topology such that the performance of the topology meets a design criterion, e.g., capable of evaluating data during a time of an emulation step. In this manner, an emulator chip designer may configure the fastpath topologies without redesigning the chip layout.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile