The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7737757 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 15, 2010

Filed:

Jul. 23, 2008
Applicants:

Derick Gardner Behrends, Rochester, MN (US);

Travis Reynold Hebig, Rochester, MN (US);

Daniel Mark Nelson, Rochester, MN (US);

Jesse Daniel Smith, Rochester, MN (US);

Inventors:

Derick Gardner Behrends, Rochester, MN (US);

Travis Reynold Hebig, Rochester, MN (US);

Daniel Mark Nelson, Rochester, MN (US);

Jesse Daniel Smith, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.


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