The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2010
Filed:
Dec. 31, 2008
Won Joon Choi, Seoul, KR;
Moon Sig Joo, Yongin-si, KR;
Heung Jae Cho, Icheon-si, KR;
Yong Soo Kim, Suwon-Si, KR;
Sung Jin Whang, Seoul, KR;
Won Joon Choi, Seoul, KR;
Moon Sig Joo, Yongin-si, KR;
Heung Jae Cho, Icheon-si, KR;
Yong Soo Kim, Suwon-Si, KR;
Sung Jin Whang, Seoul, KR;
Hynix Semiconductor Inc., Icheon-si, KR;
Abstract
A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.