The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2010

Filed:

Jan. 02, 2008
Applicants:

Thomas W. Dyer, Pleasant Valley, NY (US);

Xiangdong Chen, Poughquag, NY (US);

James J. Toomey, Poughkeepsie, NY (US);

Haining S. Yang, Wappingers Falls, NY (US);

Inventors:

Thomas W. Dyer, Pleasant Valley, NY (US);

Xiangdong Chen, Poughquag, NY (US);

James J. Toomey, Poughkeepsie, NY (US);

Haining S. Yang, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. The semiconductor device structure formed using such a semiconductor substrate includes at least one n-channel field effect transistor (n-FET) formed at the first device region having a channel that extends along the interior surfaces of the first recess, and at least one p-channel field effect transistor (p-FET) formed at the second device region having a channel that extends along the interior surfaces of the second recess.


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