Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow

Abstract

Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit resizing to enable parasitic robust designs. The worst-case parasitic corners are generated efficiently without expensive statistical computations. A performance-driven placement with simultaneous fast rough routing and device tuning generates high quality placements and compensates for layout induced performance degradations. A regression-tree based macromodeling methodology is introduced for modeling of electrical performances to enable true performance-driven layout synthesis. To improve sampling quality, an annealing-based placer can be used to perform sampling. The modeling methodology can be adapted to include automatically adjusting the device tuning ranges to meet certain model accuracy requirements.