The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7733721 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 08, 2010

Filed:

Aug. 22, 2007
Applicant:

Makoto Tabata, Tokyo-To, JP;

Inventor:

Makoto Tabata, Tokyo-To, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The disclosure concerns a semiconductor tester for testing a MUT, comprising a pattern generator; a pattern formatter; a comparator comparing a result signal from the MUT with an expectation value; a bad block memory; an AFM pre-storing pass/fail information of each of memory cells; a data compressor compressing data of pass/fail information in the AFM; a compression failure buffer memory storing data compressed; a good block register storing an address number of a good block prepared; and an address generator, wherein when the block to be compressed is a good one, the good block register sends a address number of the good block to the compress failure buffer memory.


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Tabata, Makoto. (2010). Semiconductor testing device and method of testing semiconductor memory (U.S. Patent No. 7733721). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7733721

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