The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2010

Filed:

Mar. 31, 2009
Applicants:

Jon Choy, Austin, TX (US);

David W. Chrudimsky, Austin, TX (US);

Padmaraj Sanjeevarao, Austin, TX (US);

Inventors:

Jon Choy, Austin, TX (US);

David W. Chrudimsky, Austin, TX (US);

Padmaraj Sanjeevarao, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.


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