The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Oct. 30, 2006
Zurab Khasidashvili, Hertzlia, IL;
Alexander Nadel, Haifa, IL;
Amit Palti, Ha Solelim, IL;
Ziyad Hanna, Haifa, IL;
Zurab Khasidashvili, Hertzlia, IL;
Alexander Nadel, Haifa, IL;
Amit Palti, Ha Solelim, IL;
Ziyad Hanna, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
A simultaneous satisfiability algorithm, or SSAT, allows simultaneous checks to be made efficiently for a number of literals, x, . . . ,xwhether xis true under any satisfying assignments of a formula (written in conjunctive normal form) built from the variables of these literals and other variables (or, equivalently whether xis a logical consequence of the formula). Thus, several related satisfiability checks are performed simultaneously in SSAT. Temporal induction algorithms allow the verification of the sequential behavior of finite state machines, e.g., hardware. Temporal induction algorithms may employ a SSAT solver to perform simultaneous model checking of several invariant (or safety) properties efficiently. These SSAT-based temporal induction algorithms are double-incremental, such that all learned clauses in the SSAT solver are re-used both across verified properties as well as across time frames.