The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2010

Filed:

Feb. 25, 2008
Applicants:

Brian David Barrick, Pflugerville, TX (US);

Kimberly Marie Fernsler, Round Rock, TX (US);

Dwain A. Hicks, Pflugerville, TX (US);

Takeki Osanai, Austin, TX (US);

David Scott Ray, Georgetown, TX (US);

Inventors:

Brian David Barrick, Pflugerville, TX (US);

Kimberly Marie Fernsler, Round Rock, TX (US);

Dwain A. Hicks, Pflugerville, TX (US);

Takeki Osanai, Austin, TX (US);

David Scott Ray, Georgetown, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); G06F 9/00 (2006.01); G06F 9/44 (2006.01); G06F 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.


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