The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Sep. 04, 2007
Yasushi Kameda, Yokosuka, JP;
Ken Takeuchi, Yokohama, JP;
Hitoshi Shiga, Yokohama, JP;
Takuya Futatsuyama, Yokohama, JP;
Koichi Kawai, Yokohama, JP;
Yasushi Kameda, Yokosuka, JP;
Ken Takeuchi, Yokohama, JP;
Hitoshi Shiga, Yokohama, JP;
Takuya Futatsuyama, Yokohama, JP;
Koichi Kawai, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.