The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Sep. 13, 2007
Tsutomu Yatsuo, Ibaraki, JP;
Shinsuke Harada, Ibaraki, JP;
Mitsuo Okamoto, Ibaraki, JP;
Kenji Fukuda, Ibaraki, JP;
Makoto Kato, Ibaraki, JP;
Tsutomu Yatsuo, Ibaraki, JP;
Shinsuke Harada, Ibaraki, JP;
Mitsuo Okamoto, Ibaraki, JP;
Kenji Fukuda, Ibaraki, JP;
Makoto Kato, Ibaraki, JP;
Abstract
In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers () are provided at the same distance on the right and left sides from the inverted layer () to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.