The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2010
Filed:
Apr. 24, 2008
Joon-seok Kang, Suwon-si, KR;
Sung Yi, Suwon-si, KR;
Jong-hwan Baek, Seoul, KR;
Young-do Kweon, Seoul, KR;
Joon-Seok Kang, Suwon-si, KR;
Sung Yi, Suwon-si, KR;
Jong-Hwan Baek, Seoul, KR;
Young-Do Kweon, Seoul, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.