The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2010

Filed:

Nov. 09, 2007
Applicants:

Vinay Verma, Cupertino, CA (US);

Anirban Rahut, San Jose, CA (US);

Sudip K. Nag, San Jose, CA (US);

Jason H. Anderson, Toronto, CA;

Rajeev Jayaraman, Saratoga, CA (US);

Inventors:

Vinay Verma, Cupertino, CA (US);

Anirban Rahut, San Jose, CA (US);

Sudip K. Nag, San Jose, CA (US);

Jason H. Anderson, Toronto, CA;

Rajeev Jayaraman, Saratoga, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 17/693 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.


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