The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2010

Filed:

Nov. 01, 2004
Applicants:

Akihiro Goto, Tokyo, JP;

Hironori Matsushima, Tokyo, JP;

Hiroshige Ogawa, Hyogo, JP;

Yoshio Matsuda, Hyogo, JP;

Inventors:

Akihiro Goto, Tokyo, JP;

Hironori Matsushima, Tokyo, JP;

Hiroshige Ogawa, Hyogo, JP;

Yoshio Matsuda, Hyogo, JP;

Assignees:

Mitsubishi Denki Kabushiki Kaisha, Chiyoda-Ku, Tokyo, JP;

Renesas Technology Corp., Chiyoda-Ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.


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