The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2010

Filed:

Jun. 27, 2006
Applicants:

Serge R. Bedwani, Folsom, CA (US);

Soon Seng Seh, Pulau Pinang, MY;

Siang Lin Tan, Penang, MY;

Amber Huffman, Banks, OR (US);

Chai Huat Gan, Penang, MY;

Inventors:

Serge R. Bedwani, Folsom, CA (US);

Soon Seng Seh, Pulau Pinang, MY;

Siang Lin Tan, Penang, MY;

Amber Huffman, Banks, OR (US);

Chai Huat Gan, Penang, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J 1/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.


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