The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Aug. 15, 2008
Applicants:
Bhawna Tomar, Bangalore, IN;
Krishman S. Rengarajan, Bangalore, IN;
Shetti Shanmukheshwara Rao, Bangalore, IN;
Inventors:
Bhawna Tomar, Bangalore, IN;
Krishman S. Rengarajan, Bangalore, IN;
Shetti Shanmukheshwara Rao, Bangalore, IN;
Assignee:
Elpida Memory, Inc., Chuo-ku, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract
A DLL circuit includes a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, a first controller for setting the bias current, and a second controller for selecting an output-producing variable delay element from the plural its of the variable delay elements.