The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2010
Filed:
Sep. 17, 2008
Masanori Miyata, Hyogo, JP;
Hidetsugu Miyake, Hyogo, JP;
Tadao Uehara, Hyogo, JP;
Fumihiro Fuchino, Hyogo, JP;
Mikinori Oguni, Hyogo, JP;
Akira Washino, Hyogo, JP;
Masanori Miyata, Hyogo, JP;
Hidetsugu Miyake, Hyogo, JP;
Tadao Uehara, Hyogo, JP;
Fumihiro Fuchino, Hyogo, JP;
Mikinori Oguni, Hyogo, JP;
Akira Washino, Hyogo, JP;
Ricoh Company, Ltd., Tokyo, JP;
Abstract
A disclosed semiconductor wafer includes plural semiconductor chip areas each having a color pattern capable of tracing the positional information of the semiconductor chip with respect to the semiconductor wafer. Each of the plural semiconductor chip areas arranged in a matrix manner on the semiconductor wafer includes an underlying insulation film; a wiring pattern and a frame-shaped wiring dummy pattern formed on the underlying insulation film; and plural insulation films formed on the upper side of the underlying insulation film, the wiring pattern, and the wiring dummy pattern. At least one SOG film is included in the plural insulation films, in which a color pattern in accordance with a distance from the center of the semiconductor wafer based on the SOG film is formed on a surface of the insulator film within the wiring dummy pattern in top view.