The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7719062 B1

PDF
Full Text
Expired
Date of Patent:
May. 18, 2010

Filed:

Dec. 29, 2006
Applicants:

Kevin J. Fischer, Hillsboro, OR (US);

Vinay B. Chikarmane, Portland, OR (US);

Brennan L. Peterson, Portland, OR (US);

Inventors:

Kevin J. Fischer, Hillsboro, OR (US);

Vinay B. Chikarmane, Portland, OR (US);

Brennan L. Peterson, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.


Find Patent Forward Citations

Fischer, Kevin. (2010). Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement (U.S. Patent No. 7719062). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7719062

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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