The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2010

Filed:

Jul. 04, 2005
Applicants:

Shigeharu Yamagami, Tokyo, JP;

Hitoshi Wakabayashi, Tokyo, JP;

Risho Koh, Tokyo, JP;

Kiyoshi Takeuchi, Tokyo, JP;

Masahiro Nomura, Tokyo, JP;

Koichi Takeda, Tokyo, JP;

Koichi Terashima, Tokyo, JP;

Masayasu Tanaka, Tokyo, JP;

Katsuhiko Tanaka, Tokyo, JP;

Inventors:

Shigeharu Yamagami, Tokyo, JP;

Hitoshi Wakabayashi, Tokyo, JP;

Risho Koh, Tokyo, JP;

Kiyoshi Takeuchi, Tokyo, JP;

Masahiro Nomura, Tokyo, JP;

Koichi Takeda, Tokyo, JP;

Koichi Terashima, Tokyo, JP;

Masayasu Tanaka, Tokyo, JP;

Katsuhiko Tanaka, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.


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