The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7716612 B1

PDF
Full Text
Expired
Date of Patent:
May. 11, 2010

Filed:

Nov. 20, 2006
Applicants:

Puneet Gupta, Santa Clara, CA (US);

Andrew Kahng, Del Mar, CA (US);

Saumil Shah, San Jose, CA (US);

Inventors:

Puneet Gupta, Santa Clara, CA (US);

Andrew Kahng, Del Mar, CA (US);

Saumil Shah, San Jose, CA (US);

Assignee:

Tela Innovations, Inc., Campbell, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for integrated circuit optimization to improve performance and to reduce leakage power consumption of an integrated circuit (IC). The original IC includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. The method creates an optimized standard-cell library from a standard-cell library. The standard-cell library includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. Further, an optimized IC is generated by using the optimized standard-cell library from the original IC. The optimized IC has an improved performance and reduced leakage power characteristics, as compared to the original IC.


Find Patent Forward Citations

Gupta, Puneet. (2010). Method and system for integrated circuit optimization by using an optimized standard-cell library (U.S. Patent No. 7716612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7716612

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