The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2010

Filed:

Nov. 14, 2006
Applicants:

Mike Jun, San Jose, CA (US);

Atila Ersahin, Fremont, CA (US);

Barry Mcginley, San Jose, CA (US);

Sabari Sanjeevi, San Jose, CA (US);

Inventors:

Mike Jun, San Jose, CA (US);

Atila Ersahin, Fremont, CA (US);

Barry McGinley, San Jose, CA (US);

Sabari Sanjeevi, San Jose, CA (US);

Assignee:

Photon Dynamics, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/08 (2006.01); G01R 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with the present invention, a first shorting bar drives the data lines of a TFT array having integrated gate driver circuitry. Another set of shorting bars drive the corresponding terminals of the gate driver circuitry. The pixel voltages are measured after all the pixels are charged by the driving signals applied to the shorting bars. Gate voltages are progressively applied to the gate lines by the gate driver integrated circuit (IC) via the set of shorting bars that, in turn, are driven by clock signals received from one or more pattern generators. Voltages are concurrently applied to the data lines which are connected together by the first shorting bar. The application of voltages generates a display pattern that is subsequently compared to an expected display pattern. By comparing the resulting display pattern and the expected display pattern, possible defects are detected.


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