The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2010

Filed:

Apr. 19, 2007
Applicants:

Michael Specht, Munich, DE;

Nicolas Nagel, Dresden, DE;

Franz Hofmann, Munich, DE;

Thomas Mikolajick, Dresden, DE;

Inventors:

Michael Specht, Munich, DE;

Nicolas Nagel, Dresden, DE;

Franz Hofmann, Munich, DE;

Thomas Mikolajick, Dresden, DE;

Assignees:

Qimonda AG, Munich, DE;

Qimonda Flash GmbH, Dresden, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.


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