The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2010
Filed:
Oct. 31, 2006
Michael R. Rice, Pleasanton, CA (US);
Eric A. Englhardt, Palo Alto, CA (US);
Vinay Shah, San Francisco, CA (US);
Martin R. Elliott, Round Rock, TX (US);
Robert B. Lowrance, Los Gatos, CA (US);
Jeffrey C. Hudgens, San Francisco, CA (US);
Michael R. Rice, Pleasanton, CA (US);
Eric A. Englhardt, Palo Alto, CA (US);
Vinay Shah, San Francisco, CA (US);
Martin R. Elliott, Round Rock, TX (US);
Robert B. Lowrance, Los Gatos, CA (US);
Jeffrey C. Hudgens, San Francisco, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
In a first aspect, a method of managing work in progress within a small lot size semiconductor device manufacturing facility is provided. The first method includes providing a small lot size semiconductor device manufacturing facility having (1) a plurality of processing tools; and (2) a high speed transport system adapted to transport small lot size substrate carriers among the processing tools. The method further includes maintaining a predetermined work in progress level within the small lot size semiconductor device manufacturing facility by (1) increasing an average cycle time of low priority substrates within the small lot size semiconductor device manufacturing facility; and (2) decreasing an average cycle time of high priority substrates within the small lot size semiconductor device manufacturing facility so as to approximately maintain the predetermined work in progress level within the small lot size semiconductor device manufacturing facility. Numerous other aspects are provided.