The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2010

Filed:

Nov. 23, 2005
Applicants:

Yin Jen Chen, Hsinchu, TW;

Chun Lein Su, Hsinchu, TW;

Ming Shiang Chin, Hsinchu, TW;

Chih Chieh Yeh, Hsinchu, TW;

Tzung Ting Han, Hsinchu, TW;

Inventors:

Yin Jen Chen, Hsinchu, TW;

Chun Lein Su, Hsinchu, TW;

Ming Shiang Chin, Hsinchu, TW;

Chih Chieh Yeh, Hsinchu, TW;

Tzung Ting Han, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.


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