The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2010
Filed:
Jul. 09, 2008
Applicants:
Koji Kuroki, Tokyo, JP;
Yasuhiro Takai, Tokyo, JP;
Hiroki Fujisawa, Tokyo, JP;
Inventors:
Assignee:
Elpida Memory, Inc., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract
A DLL circuit includes a delay line (CDL) () that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) () that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (). The counter control circuits control the delay line () by a linear search method, and control the delay line () by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line () is increased, a delay amount can be determined at a high speed.