The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2010
Filed:
Jun. 12, 2006
Yeol Jon, Yongin-si, KR;
Chung-ki Min, Yongin-si, KR;
Yong-sun Ko, Suwon-si, KR;
Kyung-hyun Kim, Seoul, KR;
Yeol Jon, Yongin-si, KR;
Chung-Ki Min, Yongin-si, KR;
Yong-Sun Ko, Suwon-si, KR;
Kyung-Hyun Kim, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile