The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2010
Filed:
Sep. 09, 2008
Raminda Udaya Madurawe, Sunnyvale, CA (US);
Raminda Udaya Madurawe, Sunnyvale, CA (US);
Tier Logic, Inc., Santa Clara, CA (US);
Abstract
Methods of fabricating low temperature semiconductor thin film switching devices are described. A method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line thru an insulator layer above the metal lines; forming a thin film N-type and P-type conducting transistor pair having: a contiguous amorphous silicon first geometry above the insulator layer, said first geometry including an N-type transistor region, a P-type transistor region, and a common region between the transistor regions fully covering the contact; and a gate dielectric layer above the first geometry; and a contiguous amorphous silicon second geometry above the gate dielectric layer including transistor regions that cross over the first geometry transistor regions; forming a silicide of first and second amorphous silicon geometry surfaces with a deposited metallic material, the silicided surfaces including: said second geometry surface; and said first geometry surface not covered by the second geometry, which includes the surface of the region covering the contact; depositing an insulating material; and forming conductive contacts and top metal interconnects.