The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2010

Filed:

Aug. 23, 2006
Applicants:

Satoshi Yoshida, Tokyo, JP;

Nagamasa Mizushima, Tokyo, JP;

Shinsuke Asari, Tokyo, JP;

Shigeo Kurakata, Tokyo, JP;

Makoto Obata, Chiba, JP;

Inventors:

Satoshi Yoshida, Tokyo, JP;

Nagamasa Mizushima, Tokyo, JP;

Shinsuke Asari, Tokyo, JP;

Shigeo Kurakata, Tokyo, JP;

Makoto Obata, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 5/00 (2006.01); G06K 19/06 (2006.01); G06K 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory card has external interface terminals, an interface controller connected to each of the terminals, a rewritable nonvolatile memory connected to the interface controller, and a data processor connected to the interface controller. The interface controller can perform an operation based on another command supplied from the outside in parallel with the operations of transferring a command for a data process supplied from the outside to the data processor and operating it. The interface controller has plural buffers and, after completely inputting the command for a data process from an outside to a first buffer of the plural buffers, allows data related to the other command supplied from the outside to be inputted to a second buffer of the plural buffers. The memory card can receive a command data and data to be processed subsequently from the outside without the need of waiting for the completion of the communication process between the data processor and the interface controller.


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