The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2010

Filed:

Mar. 08, 2007
Applicants:

Hidehiro Nakamura, Ibaraki-ken, JP;

Tetsuya Enomoto, Ibaraki-ken, JP;

Toshio Yamazaki, Ibaraki-ken, JP;

Hiroshi Kawazoe, Ibaraki-ken, JP;

Inventors:

Hidehiro Nakamura, Ibaraki-ken, JP;

Tetsuya Enomoto, Ibaraki-ken, JP;

Toshio Yamazaki, Ibaraki-ken, JP;

Hiroshi Kawazoe, Ibaraki-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wiring substrate () comprises an insulating base () with connection holes (), buried conductors () provided in the connection holes () without reaching a rear surface of the insulating base (), and wiring layersconnected to the buried conductors (). The buried conductors () thicken the wiring layers (), and can form aligning parts () on the rear surface of the connection holes () to be used for three-dimensional mounting structure. Each wiring layer () includes thin terminals (A), wirings (B) and thick electrodes (C). Not only the terminals (A) and wirings (B) but also the buried conductors () are raised by the same manufacturing process. A semiconductor element () is attached to the electrodes (C) of the wiring substrate ().


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