The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Apr. 05, 2006
Masayuki Arai, Tama, JP;
Kazuhiko Iwasaki, Yokohama, JP;
Satoshi Fukumoto, Kawasaki, JP;
Takeshi Shoda, Kokubunji, JP;
Junichi Nishimoto, Kawasaki, JP;
Masayuki Arai, Tama, JP;
Kazuhiko Iwasaki, Yokohama, JP;
Satoshi Fukumoto, Kawasaki, JP;
Takeshi Shoda, Kokubunji, JP;
Junichi Nishimoto, Kawasaki, JP;
Semiconductor Technology Academic Research Center, Yokohama-Shi, JP;
Abstract
An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit () and a scan chain () constructed by connecting a plurality of scan flip-flops () in a chain, the scan chain () is divided into a plurality of sub scan-chains (to) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.