The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Jul. 17, 2008
William C. Plants, Campbell, CA (US);
Suhail Zain, San Ramon, CA (US);
Joel Landry, Colorado Springs, CO (US);
Gregory W. Bakker, San Jose, CA (US);
Tomek Jasionowski, Sunnyvale, CA (US);
William C. Plants, Campbell, CA (US);
Suhail Zain, San Ramon, CA (US);
Joel Landry, Colorado Springs, CO (US);
Gregory W. Bakker, San Jose, CA (US);
Tomek Jasionowski, Sunnyvale, CA (US);
Actel Corporation, Mountain View, CA (US);
Abstract
A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.