The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Feb. 26, 2007
Hongzhong Xu, Gilbert, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Jinman Yang, Laveen, AZ (US);
Hongzhong Xu, Gilbert, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Jinman Yang, Laveen, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An electrostatic discharge (ESD) protection clamp () for I/O terminals () of integrated circuits (ICs) () comprises an NPN bipolar transistor () coupled to an integrated Zener diode (). Variations in the break-down current-voltage characteristics () of multiple prior art ESD clamps () in different parts of the same IC chip is avoided by forming the anode () of the Zener () in the shape of a base-coupled P+ annular ring () surrounded by a spaced-apart N+ annular collector ring () for the cathode () of the Zener (). Even though an angled implant () used to form the N+ annular collector ring () causes location dependent variations in the width () of the Zener space charge (ZSC) region (), the improved annular shaped clamp () always has a portion that initiates break-down at the design voltage so that variations in the width () of the ZSC region () do not cause significant variations in the clamp's current-voltage characteristics ().