The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2010

Filed:

Jan. 10, 2007
Applicants:

Takashi Noguchi, Yongin-si, KR;

Jong-man Kim, Yongin-si, KR;

Jang-yeon Kwon, Yongin-si, KR;

Kyung-bae Park, Yongin-si, KR;

Ji-sim Jung, Yongin-si, KR;

Hyuck Lim, Yongin-si, KR;

Inventors:

Takashi Noguchi, Yongin-si, KR;

Jong-man Kim, Yongin-si, KR;

Jang-yeon Kwon, Yongin-si, KR;

Kyung-bae Park, Yongin-si, KR;

Ji-sim Jung, Yongin-si, KR;

Hyuck Lim, Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/15 (2006.01); H01L 29/26 (2006.01); H01L 31/12 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
Abstract

A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.


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