The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Jan. 30, 2006
Chun-li Liu, Mesa, AZ (US);
Tushar P. Merchant, Gilbert, AZ (US);
Marius K. Orlowski, Austin, TX (US);
Matthew W. Stoker, Mesa, AZ (US);
Chun-Li Liu, Mesa, AZ (US);
Tushar P. Merchant, Gilbert, AZ (US);
Marius K. Orlowski, Austin, TX (US);
Matthew W. Stoker, Mesa, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.