The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Apr. 12, 2006
Voon-yew Thean, Austin, TX (US);
Bich-yen Nguyen, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Victor H. Vartanian, Dripping Springs, TX (US);
Ted R. White, Austin, TX (US);
Voon-Yew Thean, Austin, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Victor H. Vartanian, Dripping Springs, TX (US);
Ted R. White, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.