Semiconductor memory device having single-level cells and multi-level cells and method of driving the semiconductor memory device

Abstract

A semiconductor memory device that performs an error control operation when an error exists in an externally received command or an externally received address, and a method of driving the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array having a single-level cell area and a multi-level cell area, a command decoder which receives a command from an external source and decoding the command, an area determination unit which receives an address from an external source and determines whether a memory cell corresponding to the address belongs to either the single-level cell area or the multi-level cell area, a command flag generation unit which generates at least one enable control signal according to the decoded command and the determination result, and a logic circuit which generates a control signal for driving the memory cells included in the memory cell array or performs an error control operation, in response to the enable control signal.