The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Apr. 15, 2004
Applicant:
Frederic Reblewski, Paris, FR;
Inventor:
Frederic Reblewski, Paris, FR;
Assignee:
Mentor Graphics Corporation, Wilsonville, OR (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 17/693 (2006.01); H03K 19/00 (2006.01); H03K 19/173 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract
A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.