The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
May. 20, 2008
Maryam Ashouei, Atlanta, GA (US);
Adit D. Singh, Auburn, AL (US);
Abhijit Chatterjee, Marietta, GA (US);
Maryam Ashouei, Atlanta, GA (US);
Adit D. Singh, Auburn, AL (US);
Abhijit Chatterjee, Marietta, GA (US);
Other;
Abstract
The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.