The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2010

Filed:

Sep. 11, 2006
Applicants:

Sung-hoi Hur, Seoul, KR;

Young-min Park, Hwaseong-si, KR;

Sang-bin Song, Yongin-si, KR;

Min-cheol Park, Seoul, KR;

Ji-hwon Lee, Suwon-si, KR;

Su-youn Yi, Yongin-si, KR;

Jang-min Yoo, Seoul, KR;

Inventors:

Sung-Hoi Hur, Seoul, KR;

Young-Min Park, Hwaseong-si, KR;

Sang-Bin Song, Yongin-si, KR;

Min-Cheol Park, Seoul, KR;

Ji-Hwon Lee, Suwon-si, KR;

Su-Youn Yi, Yongin-si, KR;

Jang-Min Yoo, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.


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