The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2010

Filed:

Mar. 25, 2008
Applicants:

Hongfa Luan, Austin, TX (US);

Prashant Majhi, Austin, TX (US);

Inventors:

Hongfa Luan, Austin, TX (US);

Prashant Majhi, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/112 (2006.01); H01L 27/108 (2006.01); H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Transistors having a Hafnium-Silicon gate electrode and high-k dielectric are disclosed. A workpiece is provided having a gate dielectric formed over the workpiece, and a gate formed over the gate dielectric. The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vof the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.


Find Patent Forward Citations

Luan, Hongfa. (2010). Nmos transistors that mitigate fermi-level pinning by employing a hafnium-silicon gate electrode and high-k gate dieletric (U.S. Patent No. 7696517). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7696517

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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