The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2010

Filed:

Oct. 30, 2006
Applicants:

Bharat Chandramouli, San Jose, CA (US);

Huan-chih Tsai, Saratoga, CA (US);

Manish Pandey, San Jose, CA (US);

Chih-chang Lin, Saratoga, CA (US);

Madan M. Das, Sunnyvale, CA (US);

Inventors:

Bharat Chandramouli, San Jose, CA (US);

Huan-Chih Tsai, Saratoga, CA (US);

Manish Pandey, San Jose, CA (US);

Chih-Chang Lin, Saratoga, CA (US);

Madan M. Das, Sunnyvale, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.


Find Patent Forward Citations

Loading…